Binarzahlen addieren uberlauf
The invention relates to a binary accumulator according to the preamble of claim. Binary batteries are used in many areas of digital signal processing, for. An accumulator is generally provided from an adder and a memory associated therewith. The object of a battery is the value of an incoming binary word - hereinafter referred to as input word - hinzuzuaddieren a stored value and transmit this result to the memory.
Das jeweils gebildete Binarzahlen addieren uberlauf wird im folgenden Akkumulatorwort genannt. The word each formed is hereinafter referred Akkumulatorwort. To ensure that a newly formed Akkumulatorwort by the value range of the storage battery is displayed ie the accumulator does not overflowthe battery is generally equipped with a job number, which clearly exceeds that of the input word.
Binarzahlen addieren uberlauf, no matter how large Akkumulatorwortbreite However, an overflow can not be excluded. From Product Description for the TMSC25 Digital Signal Binarzahlen addieren uberlauf manufactured by Texas Instruments,a rechargeable battery is provided in which the overflow of the adder appear and depending on the sign of the overflow, the Binarzahlen addieren uberlauf is set to the largest possible or smallest possible value page 11, column 1, paragraph 4.
The disadvantage of this circuit lies in the fact that it reacts only after the overflow of the adder, resulting in a limitation of the operating speed of the accumulator. The invention has for its object to provide an accumulator which allows faster operation. The object is solved binarzahlen addieren uberlauf the features of claim 1. Advantageous embodiments of the invention are disclosed in the dependent claims.
An embodiment of the invention is illustrated with reference to FIGS. It consists of an adder AW parallel signal inputs E 0, E 1 for a 2-bit word and outputs parallel signal S 0 'to S 7' for an 8-bit word. Memory unit still has eight signal outputs S 0 through S 7 that represent the outputs of the accumulator AK. The signal inputs E 1, E 0 represent the input of the accumulator AK. A detector DE is at the rest to the signal outputs S binarzahlen addieren uberlauf to S 7, the most significant bits, to determine the extreme values of the 8-bit signal word corresponding to the predetermined range of values limit, connected and displays the reaching of the predetermined extreme values via line DS of the setting device to SR, in which, as shown in Fig.
The bit is set at the signal input of the memory unit SE. The stored word, hereinafter called Akkumulatorwort is shown in the embodiment in twos complement arithmetic, that is, the most significant bit of a word is negative weighted with a defined width.
In the exemplary embodiment, the input word of 2 bits. Dieses Eingangswort wird im Akkumulator AK in ein Wort mit einer Breite von 8 Bit umgewandelt und zum im Akkumulator gespeicherten alten Akkumulatorwort, das ebenfalls ein 8-Bit-Wort darstellt, addiert und binarzahlen addieren uberlauf somit das neue Akkumulatorwort.
This input word is converted in the accumulator AK in a word with a width of 8 bits and stored in the accumulator old Akkumulatorwort, which also constitutes an 8-bit word, added, and thus forms the new Akkumulatorwort. Die Bits des Akkumulatorworts sind im folgenden mit den Nummern binarzahlen addieren uberlauf bis 7 versehen. The bits of the Akkumulatorworts are provided below with the numbers 0 to 7th Das Bit Nr.
In the present battery AK the 4 most significant bits of the Akkumulatorwortes be detected and displayed, whether a predetermined minimum value or maximum value falls below or is exceeded. Since only the 4 most significant bits are detected, the detector merely indicates whether the value present at the output of the memory unit SE the minimum value binary decimal reaches or falls below, or the maximum value binary decimal reaches or exceeds.
The amount of the maximum and of the minimum value can be increased if also the bit no. If the maximum value or an overlying value is detected, the one bit of the smallest Akkumulatorwortes over the detector DE, and the setting device SR is set to 0, whose value is greater than that of maximum input word. In the exemplary embodiment, binarzahlen addieren uberlauf bit number is of Binarzahlen addieren uberlauf. Das Akkumulatorwort kann auf diese Weise bei gesetztem Bit Nr.
The Akkumulatorwort can not continue to grow in this way if bit no. Laufen Eingangsworte mit negativem Dezimalwert ein, so werden diese vom Akkumulatorwort abgezogen. Run input words with a negative decimal value, they will be binarzahlen addieren uberlauf from Akkumulatorwort. After initially falling below the maximum value of the battery AK is working correctly.
Accordingly, the opposite is true when the minimum value or a value lower than detected, and the bit no. Is set to a logical 1 2. The accumulator AK thus operates according to a process, an input word in the adder AW is added to the first in one clock period, a memory unit SE fed and pushed until the next clock period at the output of the memory unit SE and is detected there.
To prevent an overflow of the adder AW, the weight of the part of the set Akkumulatorwortes must be greater than the weight of the input word. Since binarzahlen addieren uberlauf inventive accumulator adding and detecting a Akkumulatorwortes does not take place in one clock period, but the detection is carried out is delayed by one clock period, the clock frequency may be increased for a given adder and for a given storage unit.
The Akkumulatorwort binarzahlen addieren uberlauf be shown next to the display in two complementary arithmetic in another form, namely z.
In this case occur in some valences instead of two only one bit on and a subsequent Verschmelzungsaddierer must form from this sum binarzahlen addieren uberlauf and each carry bit in binarzahlen addieren uberlauf weights a single sum word. The upper carry input C of the full adder VA 0 is set. Instead of the full adder VA 0, a half adder may be disposed.
The carry output of binarzahlen addieren uberlauf full adder VA 7 is not used. The Q output of each D flip-flop FF 1 to FF 7 is each returned to an adder binarzahlen addieren uberlauf B of that full adder with which it via the signal output S connected is. This linking the transformation of the binarzahlen addieren uberlauf input word is done in the 8-bit wide Akkumulatorwort. For detecting the four most significant bits are used.
The smallest possible value of the four most significant bits, namely This means that the minimum value is detected. Is located at the output for all other values of the four highest weight bits of the AND circuit G 1, a logic 0. This means that the maximum value is detected. Is located at the output for all other values of the four highest weight bits of the AND circuit G 2 binarzahlen addieren uberlauf a logic 0.
In this case, the input signal IN 1 is turned on and the bit no. Minimum value is detected, is located on the input signal IN 1 is a 1 indicates the maximum value is detected, is located on the input signal IN 0 is a 0 on.
In the event that neither the minimum nor the maximum value can be detected, located binarzahlen addieren uberlauf the control input of the selector SEL is a logic 0 and the input IN 0 of Selektros SEL is turned on. In the circuit example of the adder consists of eight 1-bit full adders, in principle it may also consist of a combination of other adders such.
As two 4-bit full adders, or a 8-bit full adder are made. The use of eight D-type flip-flop as a storage unit SE arises in connection with the eight 1-bit full adders as an advantageous embodiment kar. In principle, another storage device can be used. The detector and binarzahlen addieren uberlauf setting means may also be realized in any manner, a flip-flop with two set inputs an alternative to the circuit example in place of the D flip-flop FF 2 are arranged, in which the outputs of the logical AND binarzahlen addieren uberlauf G 1 and G 2 are each supplied to a set input of the D flip-flops.
The addition mechanism is connected to the memory unit, with which an input word is added to a stored word. The detector checks whether the values of the stored word lie within a predetermined value range and, where the value of the stored word are outside the predetermined value range, it generates a set signal.
The detector DE only checks extreme values of the stored word, and where values are present outside the predetermined value range a part of the stored word is set via the set device SRwhereby the wt. Binarzahlen addieren uberlauf detector is directly connected to the signal output of the memory unit SE and the set device is connected to a signal input or a set input of the memory. Accumulator according to one of claims 1 or 2, characterized in that the detector DE directly to the signal output binarzahlen addieren uberlauf the memory unit SE and the setting means SR, SEL having a signal input or a reset input of the memory unit SE connected is.
Accumulator according to one of claims 1 to 3, characterized in that the stored word is represented in twos binarzahlen addieren uberlauf arithmetic. Accumulator according to binarzahlen addieren uberlauf of claims 1 to 4, characterized in that the adder AWa plurality of series-connected 1-bit full adder VA 0 to VA 7each with a, in its entirety, the memory unit SE forming, D-flip-flop FF 0 to FF 7in that binarzahlen addieren uberlauf setting means SR comprises a selector SEL having two signal inputs IN 0, IN 1 is formed by the detector DE is activated and whose first signal input Binarzahlen addieren uberlauf 0 with the signal output of a 1-bit full adder AV 2whose second signal input IN 1 to the set output of the detector DE and its signal output connected to the signal input of a D-type flip- flop FF 2 is connected.
DE DEA1 en Binary accumulator with overflow protection - comprises addition mechanism, memory unit, detector and set unit suitable for processor or digital filter. Process for determining an overflow to the format of the result of an arithmetic operation carried out on two operands. Delay circuit with integrated insulated-layer binarzahlen addieren uberlauf transistor for digital signals, and application of the same to colour television receivers.
Digital fuzzy logic controller - has parallel processing stages to operate on specific parameters for fast operation. A method for real time determination of the offset portion of a measurement signal. Circuit arrangement to address functional units of a data processing system via an address bus. Method and device for combining variable-length operands in data processing systems. Device for alteration of the duty ratio or the pulse number density of a signal sequence.
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